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W83791SD/ W83791SG WINBOND H/W MONITORING IC
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Publication Release Date: January 18, 2005 Revision 1.1
W83791SD/W83791SG
Revision History
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PAGES
DATES
VERSION
VERSION ON WEB
MAIN CONTENTS
1 2 3 4 5 6 7
n.a. n.a. n.a. n.a. 01/Jan 02/Apr 05/Jan 0.5 1.0 1.1
n.a. n.a. 1.0 1.1
All version before 0.50 are for internal use. First publication. Change all version include version on web site to 1.0 Add lead-free package version
Please note that all data and specifications are subject to change without notice. All the trademarks of products and companies mentioned in this data sheet belong to their respective owners.
Life Support Applications
These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
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W83791SD/W83791SG
Table of Contentswww..com 1.
GENERAL DESCRIPTION ......................................................................................................... 1 FEATURES ................................................................................................................................. 1 KEY SPECIFICATIONS .............................................................................................................. 2 PIN CONFIGURATION ............................................................................................................... 2 PIN DESCRIPTION..................................................................................................................... 3 FUNCTION DESCRIPTION ........................................................................................................ 4 6.1 Speech Function ............................................................................................................. 4
6.1.1 6.1.2 6.1.3 6.1.4 General Description..........................................................................................................4 Event Trigger Queue ........................................................................................................4 Connection of EEPROM...................................................................................................5 Speaker Output ................................................................................................................6
2. 3. 4. 5. 6.
7.
CONTROL AND STATUS REGISTER ....................................................................................... 6 7.1 Speech Flash Memory Address Registers Index 00h-02h (Bank 0).......................... 6 7.2 Speech Flash Memory Data Registers Index 03h-06h (Bank 0) ............................... 6 7.3 Event Trigger Timeout Register Index 08h (Bank 0).................................................. 7 7.4 Speech Programmable Trigger Register Index 09h (Bank 0).................................... 8 7.5 Speech Input Trigger Property Register Index 0Ah (Bank 0) .................................... 8 7.6 Speech Flash Memory Read Data Registers Index 0Dh-0Eh (Bank 0)..................... 8 7.7 User Defined Registers Index 18h-1Ch (Bank 0)....................................................... 9 7.8 Speech Control Register 1 Index 1Fh (Bank 0) ......................................................... 9 7.9 Serial Bus Address Register Index 48h (Bank 0)....................................................... 9 7.10 Device ID Index 49h (Bank 0) .................................................................................... 9 7.11 Disable Abnormal BEEP Control Register Index 4Dh (Bank 0)............................... 10 7.12 High Byte Access Index 4Eh (Bank 0) ..................................................................... 10 7.13 Winbond Vendor ID Index 4Fh (Bank 0) .................................................................. 10 7.14 Winbond Test Register Index 50h - 55h (Bank 0).................................................... 10 7.15 Chip ID -- Index 58h (Bank 0) ....................................................................................... 10 7.16 Speech Flash Memory Read Data Registers Index A4h-A5h (Bank 0) ................... 11 7.17 Flash Page count Index A7h (Bank 0) ..................................................................... 11 ELECTRICAL CHARACTERISTICS......................................................................................... 11 8.1 Absolute Maximum Ratings .......................................................................................... 11 8.2 DC Characteristics ........................................................................................................ 11 8.3 AC Characteristics ........................................................................................................ 13
8.3.1 Serial Bus Timing Diagram.............................................................................................13
8.
9. 10. 11.
HOW TO READ THE TOP MARKING...................................................................................... 14 PACKAGE SPECIFICATION .................................................................................................... 15 APPLICATION CIRCUITS ........................................................................................................ 16
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Publication Release Date: January 18, 2005 Revision 1.1
W83791SD/W83791SG
1. GENERAL DESCRIPTION
W83791SD/SG www..com is a programmable speech synthesizer with 9-bit current DAC output that can connect to speaker or LINE_OUT by the AC'97 audio codec. It supports 1 CPU present or absent event trap, 5 external event traps, and 127 internal programmable event traps to trigger maximum 133 different speech output. If more than two events happen simultaneously, the priority set is: SLOTOCC# > EVNTRP1 > EVNTRP2 > EVNTRP3 > EVNTRP4 > EVNTRP5 > 127 Programmable events (Bank0 index 09h). For the application of error messages from BIOS, 127 Programmable events are enabled with a watch dog timer. The time interval is programmable and events will be triggered when time out. External flash memory interface with Winbond W55FXX is flexible to change warning voice message and support on-line programming flash data through I2CTM interface. An external resistor is added to provide ring oscillator. Through the application software or BIOS, the users can edit and change the voice database in the serial flash chip by themselves under O.S. A free Windows AP --- Voice EditorTM is provided for the voice editing, which can accept the *.wav file as the voice database resource. Users can replace the voice with which they like through the S/W. W83791SD/SG also provides two addresses setting pins A0 & A1 for different I2CTM address and can be connected up to 4 devices if necessary.
2. FEATURES
Speech Item
* * * * * * * * * * Programmable speech synthesizer New high fidelity synthesis algorithm Build in 8-bit current D/A converter Instruction cycle 400 S typically Section control provided in each voice section Variable frequency: 4.8/6/8/12 KHz External resistor for ring oscillator 1 CPU present or absent trigger input 5 External trigger inputs 127 Internal programmable trigger inputs with a watch dog timer Programmable 0-255 seconds timeout trigger inputs
General
* I2CTM serial bus interface * 2 pins (A0, A1) to provide selectable address setting for application of multiple devices (up to 4 devices) wired through I2CTM interface * Winbond hardware monitoring application software (Voice EditorTM) support, for both Windows 95/98/ME/2000 and Windows NT 4.0/5.0 * Internal clock Oscillator with 3M Hz * 5V VDD operation
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Publication Release Date: January 18, 2005 Revision 1.1
W83791SD/W83791SG
Package
* 48-pin www..com LQFP
3. KEY SPECIFICATIONS
* Supply Voltage * Operating Supply Current 5V 5 mA typ.
4. PIN CONFIGURATION
+ 3.3 GGV GGGV V G G V NN I NNNDD N NN D DDNDDDDD D DC D
NC GND GND GND VDD NC NC NC EVNTRP1 EVNTRP2 EVNTRP3 EVNTRP4
36 35 34 33 37 38 39 40 41 42 43 44 45 46 47 48 1 2 3 4
32 31 30
29
28 27
26 25 24 23 22 21 20
W83791SD
19 18 17 16 15 14
5
6
7
8
9
10 11
12
13
VDD NC SDA SC L VDD VDD VDD VDD GND SLOTOCC# GND VDD
E E RACD VOEDLA NP XDKT T T ROA R U P T 5
C T R L
M O D E
SAAV P01D E D A K E R
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W83791SD/W83791SG
5. PIN DESCRIPTION
www..com I/O12t
I/O12ts I/OD8ts OUT12 INt INts AIN
- TTL level bi-directional pin with 12 mA source-sink capability - TTL level and schmitt trigger with 12 mA source-sink capability - TTL level and schmitt trigger open drain output with 8 mA sink capability - Output pin with 12 mA source-sink capability - TTL level input pin - TTL level input pin and schmitt trigger - Input pin (Analog)
PIN NO. 1 2 3 4 TYPE IN t IN t IN t OUT12 DESCRIPTION Event trapping to selection speech output sound. End of Process signal input from cascaded Flash. Resistor (Rosc) connects to VSB to adjust ring oscillator frequency. Speech address pulse output, connect to W55FXX. When this pin translates from logic high to logic low, it will latch the data pin 6 and shift it into a speech flash address counter. Speech clock output, for speech data read-out and write-in, connect to W55FXX. When this pin translates from logic high to logic low, the data pin 6 will be latched by this clock. Serial data input/output, connect to W55FXX. The pin is latched by CLKOUT and ADDR acted as speech data and address respectively. Output clock numbers of this pin decide which mode is selected. Connect to W55FXX. Output mode signal to W55FXX serial Flash. Current type output driving an external speaker. The function is only working in VSB 5V OK. I2C device address bit0 trapping during 5VDD power on. I2C device address bit1 trapping during 5VDD power on. +5V VDD pins.
PIN NAME EVNTRP5 EOP REXT ADDR
CLKOUT
5
OUT12
DATA CTRL MODE SPEAKER A0 A1 VDD (5V)
6 7 8 9 10 11 12, 13, 17, 18, 19, 20, 24, 25, 29, 30, 41 14, 16, 27, 28, 31, 32, 33, 35, 36, 38, 39, 40 15 23, 26, 37, 42, 43, 44 21 22 34 45-48
I/O12t OUT12 OUT12 OUT12 INts INts POWE R GROU ND INts
GND SLOTOCC# NC SCL SDA +3.3VIN EVNTRP1-4
Ground pins CPU presence signal. 0 means CPU is present. 1 means CPU is absent. No connect.
INts I/OD8ts AIN I/O12ts
Serial Bus Clock. Serial Bus bi-directional Data. 0V to 4.096V FSR Analog Inputs. Event trapping to selection speech output sound.
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W83791SD/W83791SG
6. FUNCTION DESCRIPTION
www..com 6.1 Speech
Function
6.1.1
General Description
The W83791SD/SG is a derivative of Winbond's PowerSpeechTM synthesizers. There are up to 5 hardware trigger inputs and 128 programmable software event trigger inputs. If more than two events happen simultaneously, the priority set by the internal H/W is: SLOTOCC# > EVNTRAP1 > EVNTRAP2 > EVNTRAP3 > EVNTRAP4 > EVNTRAP5 > TRIGREG (Index 09h) 128 events. Software trigger is able to accommodate 128 event triggers, with timeout register (index 08h) enabled in advance for allowance of time on detecting devices. That is, once the system's power is on, BIOS can fill trigger event and speech voice will not be sent until the system fails owing to timeout. In addition, to prevent events from taking place simultaneously.
6.1.2
Event Trigger Queue
W83791SD/SG provides 8 byte FIFO queue to store event trigger, i.e., the first 8 event can be served by speech and speech will clear FIFO queue after service. Coding of Speech program must assign correct CPU_MODE event vector to issue correct speech voices correspondent to speech trigger events. For example, CPU_MODE event vector =1 represents absence of CPU, then coding speech with CPU is absent voice. When W83791SD/SG detects no CPU exists, it will send vector = 1 to speech synthesizer and play this voice data. Following is the block diagram of the 8-Byte event trigger queue.
Enable Timeout CLK 1 HZ
(Index 0Ah, b6)
8-bit Counter Timeout Comparator
TRIG_REG Event Trigger Data
Trigger Timeout Register
(Index 08h)
(Index 09h, b6~0)
8-Byte Event Trigger Queue
Figure 1. Event trigger Queue
For example: As BIOS usually has POST (Power On Self Test) program, then it will test every item step by step if no failure takes place, however, if it detects a failure on a specific item, it will hang on there. Therefore, BIOS could write timeout value to register 08h and start timer setup speech trigger event (register 09h), then BIOS test program starts. Whenever the system is hang on specific item such as DRAM testing, W83791SD/SG would say "DRAM test fails" after the timeout previously set at CR [08h]. On the contrary, if DRAM test is ok, then BIOS could update the timeout value and proceed to the next test program.
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W83791SD/W83791SG
Below is the speech CPU_MODE table of W83791SD/SG.
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CPU_MODE ITEM
DEFINITION
VECTOR (H)
POI SLOTOCC EVNTRAP1(TG1) EVNTRAP2 EVNTRAP3 EVNTRAP4 EVNTRAP5 TRIGREG
Reserverd CPU present or absent Hardware trgger1 Hardware trgger2 Hardware trgger3 Hardware trgger4 Hardware trgger5 I2C setting software trigger Table 1 CPU_MODE
0,32 1 2 3 4 5 6 80-FF
6.1.3
Connection of EEPROM
As described previously the W83791SD/SG could connect W55FXX to store voice data. To expand the storage capacity, users could select more than one W55FXX to connect together. The maximum capacity could be up to 16Mbit. Following is the connection chart of W55FX with W83791SD/SG.
EEPROM
DATA ADDR CLK CTRL MODE EOP
EEPROM
DATA ADDR CLK CTRL MODE EOP
SLOTOCC# EVTTRAP 1: 5
DATA ADDR CLK CTRL MODE EOP
Speech Synthesizer (W83791SD/SG)
9-bit DAC
SPEAKER
Internal programmable trigger
Hardware monitor status trigger
Figure 2 Speech Function Diagram
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Publication Release Date: January 18, 2005 Revision 1.1
W83791SD/W83791SG
6.1.4 Speaker Output Speech www..com output pin is an 8 bit Current D/A converter, with which loading is needed. The resistor could range from 510~1K ohm and bipolar junction transistor could be a low power NPN type bipolar with of 120 - 160. Usually, an 8050D transistor is appropriate. The spec of the speaker is 8. Besides,
SPK can also connect to AC97 codec chip Line_Out. C is decouple capacitor and is usually 200p- 0.01uF.
8 ohm speaker SPK R C 8050D, NPN transistor
Figure. 3
7. CONTROL AND STATUS REGISTER
7.1 Speech Flash Memory Address Registers Index 00h-02h (Bank 0)
Power on default: 00h
INDEX NAME ATTRIBUTE DESCRIPTION
00h 01h 02h
SPEECHA0 SPEECHA1 SPEECHA2
R/W R/W R/W
Speech Flash Address 0. Set speech flash programming address bits [7:0]. Speech Flash Address 1. Set speech flash programming address bits [15:8]. Speech Flash Address 2. Set speech flash programming address bits [23:16].
7.2 Speech Flash Memory Data Registers Index 03h-06h (Bank 0)
Power on default: 00h
INDEX NAME ATTRIBUTE DESCRIPTION
03h 04h 05h 06h
SPEECHD0 SPEECHD1 SPEECHD2 SPEECHD3
R/W R/W R/W R/W
Speech Flash Data data bits [7:0]. Speech Flash Data data bits [15:8]. Speech Flash Data data bits [23:16]. Speech Flash Data data bits [31:24].
0. Set speech flash programming 1. Set speech flash programming 2. Set speech flash programming 3. Set speech flash programming
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W83791SD/W83791SG
Power on default: 00h
www..com BIT
NAME
ATTRIBUT E
DESCRIPTION
7 6:4
PROG_ACTIVE Reserved
R/W
3:0
PROGMODE
R/W
Program Active Command. If set this bit to 1, the serial flash will be active according the Flash Program Mode. Reading this bit, the bit will return a Serial Flash Busy (SER_BUSY). And this is pulse, if read this bit show "0" Reserved. Flash Program Mode FLASHCTRL[3:0] 0000b No action 0001b Program mode 0010b Erase all 0011b Page code 0100b Erase 4K bytes 0101b Erase 16K bytes 0110b Page code read out 0111b Read flash data
Program procedure: 1. Set Flash address (3-bytes) 2. Set Flash Data (4-bytes) 3. Set Flash control "Program mode" 4. Set program command active (PROG_ACTIVE) Erase 4K: 1. Set Flash Address (must be 4K address boundary) 2. Set Flash control register
7.3 Event Trigger Timeout Register Index 08h (Bank 0) Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7:0
TRIG_TIME
R/W
Event Trigger Timeout Timer Setting. When software or firmware write trigger event, that don't write to speech queue until this register is timeout. This unit is Second. Default is 00, that is, the software event doesn't need to wait then write to sound event queue. Note that, this function is controlled by Speech Input Property (Index 0Ah).
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Publication Release Date: January 18, 2005 Revision 1.1
W83791SD/W83791SG
7.4 Speech Programmable Trigger Register Index 09h (Bank 0) Power www..com on default: 80h
BIT NAME ATTRIBUTE DESCRIPTION
7
TR_RDY
RO
6:0
TRIG_REG
R/W
Programmable Trigger Register Ready. If return to 1, the software or firmware can write next event to trigger register. If return to 0, the software or firmware cannot write trigger event to event queue, that is, the timer is not timeout yet. Speech Programmable Trigger Register. The software or firmware can set these bits to trigger speech sound. The vectors of sound trigger are shown as follows. If the bit of trigger register ready is logic 0, this trigger register will be ignored. Therefore, the bit of the trigger ready should be read before programming this register. TRIG_REG<6:0> Speech Sound Vector 00h Vector 80h (1000_0000b) (=80h+00h) 01h Vector 81h (1000_0001b) (=80h+01h) 02h Vector 82h (1000_0010b) (=80h+02h) : : Vector (80h+n) N : : 7Eh Vector FEh (1111_1110b) (=80h+7Eh) 7Fh Vector FFh (1111_1111b) (=80h+7Fh)
7.5 Speech Input Trigger Property Register Index 0Ah (Bank 0) Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4:0
En_Program En_Timeout Busy EVNTRAP51 Polarity
R/W WO RO R/W
Enable W83791SD/SG to program external serial flash memory. Enable Software/Firmware Trigger Timeout Function. This bit sets the Event Trigger Timeout Function in Index 08h. If read this bit return "1" means SPKOUT is in busy. Write `0' the EVNTRAP5-1 will positive edge trigger, Write `1' will negative edge trigger. Default is `0'.
7.6 Speech Flash Memory Read Data Registers Index 0Dh-0Eh (Bank 0)
Power on default: 00h
INDEX NAME ATTRIBUTE DESCRIPTION
0Dh 0Eh
SPEECHRD0 SPEECHRD1
RO RO
Speech Flash Read Data 0. Speech flash reading data bits [7:0]. Speech Flash Read Data 1. Speech flash reading data bits [15:8].
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W83791SD/W83791SG
7.7 User Defined Registers Index 18h-1Ch (Bank 0)
User defined www..com registers. Write a data to the mapped register will return a prior written data when read this mapped register.
7.8 Speech Control Register 1 Index 1Fh (Bank 0)
Power on default: 00h
BIT NAME ATTRIBUTE DESCRIPTION
7 6 5 4 3 2 1:0
Dis_SLOC_SPK Dis_ET5_SPK Dis_ET4_SPK Dis_ET3_SPK Dis_ET2_SPK Dis_ET1_SPK Reserved
R/W R/W R/W R/W R/W R/W
Disable SPEECH output from SLOTOCC# if the CPU is absent. Write 1, disable SPEECH output. Default 0. Disable SPEECH output from EVNTRP5 if a transition occurs at pin. Write 1, disable SPEECH output. Default 0. Disable SPEECH output from EVNTRP4 if a transition occurs at pin. Write 1, disable SPEECH output. Default 0. Disable SPEECH output from EVNTRP3 if a transition occurs at pin. Write 1, disable SPEECH output. Default 0. Disable SPEECH output from EVNTRP2 if a transition occurs at pin. Write 1, disable SPEECH output. Default 0. Disable SPEECH output from EVNTRP1if a transition occurs at pin. Write 1, disable SPEECH output. Default 0.
7.9 Serial Bus Address Register Index 48h (Bank 0)
Power on default: 0010_11xx.
BIT NAME ATTRIBUTE DESCRIPTION
7 6-0
Reserved SMBADDR1 R/W
Reserved. Serial Bus Address <7:1> for general index registers. The address bit 0 and bit 1 are trapped by the pin 10 and pin 11, respectively.
7.10 Device ID Index 49h (Bank 0)
Power on default: 0001_000x
BIT NAME ATTRIBUTE DESCRIPTION
7-1 0
DID<6:0> Reserved
Read only
Device ID<6:0>, W83791D version ID that differentiates chip serial product number. This default value is 0010000b, that means is 1.0.
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Publication Release Date: January 18, 2005 Revision 1.1
W83791SD/W83791SG
7.11 Disable Abnormal BEEP Control Register Index 4Dh (Bank 0)
Power www..com on
BIT
default [7:0]: 0001_0101; Reset by MR.
NAME ATTRIBUTE DESCRIPTION
7
DIS_ABN
R/W
Disable power-on abnormal the monitor voltage including Vcore, and +3.3V. If these voltages exceed the limit value, the pin of BEEP (Open Drain) will drive 300Hz and 600Hz frequency signal. Write 1, the frequency will be disabled. Default 0. After power on, the system should set 1 to this bit to 1 in order to disable BEEP. Reserved.
6:0
Reserved
7.12 High Byte Access Index 4Eh (Bank 0)
Power on default [7:0] 1000_0000b; Reset by MR.
NAME ATTRIBUTE DESCRIPTION
7 6:0
HBACS Reserved
R/W
High byte access. Set to 1, access Register 4Fh high byte register. Set to 0, access Register 4Fh low byte register. Default 1. Reserved
7.13 Winbond Vendor ID Index 4Fh (Bank 0)
Power on default: A3h
BIT NAME ATTRIBUTE DESCRIPTION
7:0
Vendor ID
Read Only
Vendor ID low byte if CR4E.bit7=0. Default A3h. Vendor ID high byte if CR4E.bit7=1. Default 5Ch.
7.14 Winbond Test Register Index 50h - 55h (Bank 0)
These Registers is reserved for Winbond test only. Users do not use these registers.
7.15 Chip ID -- Index 58h (Bank 0)
Power on default: 71h
BIT NAME ATTRIBUTE DESCRIPTION
7-0
CHIPID
Read Only
Winbond Chip ID. Read this register will return 71h.
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W83791SD/W83791SG
7.16 Speech Flash Memory Read Data Registers Index A4h-A5h (Bank 0)
Power www..com on
INDEX
default: 00h
NAME ATTRIBUTE DESCRIPTION
A4h A5h
SPEECHRD2 SPEECHRD3
RO RO
Speech Flash Read Data 2. Speech flash reading data bits [23:16]. Speech Flash Read Data 3. Speech flash reading data bits [31:24].
7.17 Flash Page count Index A7h (Bank 0)
Power on default: 00h; Reset by MR.
BIT NAME ATTRIBUTE DESCRIPTION
7-5 4-0
Reserved Page count RO
Reserved Flash (W55FXX) size of each page is 512K, so read these bits may know the flash size when finish page coding program.
8. ELECTRICAL CHARACTERISTICS
8.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Power Supply Voltage Input Voltage Operating Temperature Storage Temperature
-0.5 to 7.0 -0.5 to VDD+0.5 0 to +70 -55 to +150
V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
8.2 DC Characteristics
(Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V)
PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O12t - TTL level bi-directional pin with source-sink capability of 12 mA Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage VIL VIH VOL VOH ILIH ILIL 2.4 +10 -10 2.0 0.4 0.8 V V V V A A IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V
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Publication Release Date: January 18, 2005 Revision 1.1
W83791SD/W83791SG
DC Characteristics, continued
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PARAMETER
SYM.
MIN.
TYP.
MAX.
UNIT
CONDITIONS
I/O12ts - TTL level bi-directional pin with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Output Low Voltage Output High Voltage Input High Leakage Input Low Leakage Output Low Voltage Output High Voltage Output Low Voltage Output Low Voltage Output Low Voltage INt - TTL level input pin Input Low Voltage Input High Voltage Input High Leakage Input Low Leakage Input Low Threshold Voltage Input High Threshold Voltage Hysteresis Input High Leakage Input Low Leakage VIL VIH ILIH ILIL VtVt+ VTH ILIH ILIL 0.5 1.6 0.5 0.8 2.0 1.2 +10 -10 2.0 +10 -10 1.1 2.4 0.8 V V A A V V V A A VIN = VDD VIN = 0 V VDD = 5 V VDD = 5 V VDD = 5 V VIN = VDD VIN = 0 V VtVt+ VTH VOL VOH ILIH ILIL VOL VOH VOL VOL VOL 2.4 0.4 0.4 0.4 2.4 +10 -10 0.4 0.5 1.6 0.5 0.8 2.0 1.2 0.4 1.1 2.4 V V V V V A A V V V V V VDD = 5 V VDD = 5 V VDD = 5 V IOL = 12 mA IOH = - 12 mA VIN = VDD VIN = 0V IOL = 12 mA IOH = -12 mA IOL = 8 mA IOL = 12 mA IOL = 48 mA
OUT12t - TTL level output pin with source-sink capability of 12 mA
OD8 - Open-drain output pin with sink capability of 8 mA OD12 - Open-drain output pin with sink capability of 12 mA OD48 - Open-drain output pin with sink capability of 48 mA
INts - TTL level Schmitt-triggered input pin
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W83791SD/W83791SG
8.3 AC Characteristics
www..com 8.3.1
Serial Bus Timing Diagram
t SCL
t
tR R
SCL
t HD;SDA
t SU;DAT t SU;STO
SDA IN
VALID DATA
t HD;DAT
SDA OUT Serial Bus Timing Diagram
Serial Bus Timing
PARAMETER SYMBOL MIN. MAX. UNIT
SCL clock period Start condition hold time Stop condition setup-up time DATA to SCL setup time DATA to SCL hold time SCL and SDA rise time SCL and SDA fall time
t SCL tHD;SDA tSU;STO tSU;DAT tHD;DAT tR tF
-
10 4.7 4.7 120 5 1.0 300
uS uS uS nS nS uS nS
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Publication Release Date: January 18, 2005 Revision 1.1
W83791SD/W83791SG
9. HOW TO READ THE TOP MARKING
The top www..com marking of W83791SD
W 83791SD 225G D
Left: Winbond logo 1st line: part number W83791SD, D means LQFP (Thickness = 1.4 mm). 2nd line: Tracking code 025 GD 225: packages made in 2002, week 25 G: assembly house ID; A means ASE, O means OSE, G means Greatek. D: IC revision; D means version D. The top marking of W83791SG
W 83791SG 225G D
Left: Winbond logo 1st line: part number W83791SG; G means lead-free package. 2nd line: Tracking code 225 GD 225: packages made in 2002, week 25 G: assembly house ID; A means ASE, O means OSE, G means Greatek D: IC revision; D means version D.
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W83791SD/W83791SG
10. PACKAGE SPECIFICATION
48-pin www..com LQFP
HD D
36 25
Symbol
Dimension in inch Min. Nom. Max.
Dimension in mm Min.
--0.05 1.35 0.17 0.09
Nom.
----1.40 0.20 --7.00 7.00 0.50 9.00 9.00
Max.
1.60 0.15 1.45 0.27 0.20
37
24
E
HE
48
13
1
e
b
12
A A1 A2 b c D E e HD HE L L1 y 0
Notes:
c
0.45
0.60 1.00
0.75
--0
0.08 3.5
--7
A2 A1 y
A
Seating Plane
See Detail F
L L1 Detail F
1. Dimensions D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeters 4. General appearance spec. should be based on final visual inspection spec.
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Publication Release Date: January 18, 2005 Revision 1.1
W83791SD/W83791SG
11. APPLICATION CIRCUITS
3VCC R1 R 4.7K 330 R2 R 4.7K SMDAT SMCLK R4 R 330
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SDA SCL
R R3
+3.3V GND R5 10K
GND GND GND VCC VCC GND
GND GND
VCC
U1
3VCC
36 35 34 33 32 31 30 29 28 27 26 25
GND GND +3.3VIN GND GND GND VDD VDD GND GND NC VDD
GND
EVNTRAP5 EOP REXT ADDR CLKOUT DATA CTRL MODE SPEAKER A0 A1 VDD
EVNTRAP1 EVNTRAP2 EVNTRAP3 EVNTRAP4
37 38 39 40 41 42 43 44 45 46 47 48
NC GND GND GND VDD NC NC NC EVNTRAP1 EVNTRAP2 EVNTRAP3 EVNTRAP4
VDD NC SDA SCL VDD VDD VDD VDD GND SLOTOCC# GND VDD
24 23 22 21 20 19 18 17 16 15 14 13
VCC SDA SCL
R6 R 10K SLOTOCC#
VCC
(From PII/PIII CPU)
0: means CPU is present 1: means CPU is absent
GND GND VCC C1 VCC
CAP 10u W83791SD
C2 CAP 0.1u
EVNTRAP5
A0 A1 VCC
1 2 3 4 5 6 7 8 9 10 11 12
EOP
SPK MODE CTRL DATA CLKOUT ADDR R8 VCC 220K R
VCC R7 A0 4.7K R9 4.7K WINBOND ELECTRONICS CORP. Title Size B Date: W83791SD Application Circuit Document Number Tuesday, May 29, 2001 Sheet 1 of 3 Rev 0.1
A1
NOTE :
The EVNTRAP1-5 trigger inputs default are low to high active.
I2C slave address is 0x5A.
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W83791SD/W83791SG
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SPK R10 510
SPKOUT SPKOUT
C3
1uF/16V
VCC C4 LINE_OUT_L LS1 1uF/16V 8 ohm SPEAKER SPKOUT C6 0.1uF Q1 NPN 8050D LINE_OUT_R 1uF/16V R12 470K C8 100pF R11 470K C5 100pF
J1
From AC' 97 Codec (W83972D)
LINE_OUT
C7
(SPEECH FUNCTION)
(SPEECH FUNCTION)
Note : Select SPEECH Function by one of two cricuits.
Connect to serial FLASH EEPROM (W55FXX)
VCC EOP
VCC
U2 EOP CTRL EOP CTRL 1 2 3 ADDR ADDR 4 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5 CKOUT DATA 1 CLKOUT DATA ADDR CTRL 2 3 4 MODE MODE U3 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5 CKOUT DATA MODE 1 2 3 4 U4 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5 1 2 3 4 U5 EOP CTRL VSS ADDR MODE VDD CLK DATA W55F10 8 7 6 5
Connect 1 FLASH
Connect 2 or more FLASH
WINBOND ELECTRONICS CORP. Title W83791SD Application Circuit Size Document Number Custom Date: Tuesday, May 29, 2001 Sheet 2 of 3 Rev 0.1
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Publication Release Date: January 18, 2005 Revision 1.1
W83791SD/W83791SG
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REV 0.1
Decription First Publication
WINBOND ELECTRONICS CORP. Title Size A Date: W83791SD Application circuit Document Number Tuesday, May 29, 2001 Sheet 3 of 3 Rev 0.1
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W83791SD/W83791SG
www..com
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owner.
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Publication Release Date: January 18, 2005 Revision 1.1

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